Parallel semiconductor device simulation: from power to 'atomistic' devices

Asenov, A., Brown, A.R. and Roy, S. (1998) Parallel semiconductor device simulation: from power to 'atomistic' devices. In: International Workshop on Computational Electronics, Osaka, Japan, 19-21 October 1998, pp. 58-61. ISBN 0780343697 (doi:10.1109/IWCE.1998.742707)



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This paper discusses various aspects of the parallel simulation of semiconductor devices on mesh connected MIMD platforms with distributed memory and a message passing programming paradigm. We describe the spatial domain decomposition approach adopted in the simulation of various devices, the generation of structured topologically rectangular 2D and 3D finite element grids and the optimisation of their partitioning using simulated annealing techniques. The development of efficient and scalable parallel solvers is a central issue of parallel simulations and the design of parallel SOR, conjugate gradient and multigrid solvers is discussed. The domain decomposition approach is illustrated in examples ranging from `atomistic' simulation of decanano MOSFETs to simulation of power IGBTs rated for 1000 V.

Item Type:Conference Proceedings
Glasgow Author(s) Enlighten ID:Asenov, Professor Asen
Authors: Asenov, A., Brown, A.R., and Roy, S.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Device Modelling Group
Publisher:Institute of Electrical and Electronics Engineers
Copyright Holders:Copyright © 1998 Institute of Electrical and Electronics Engineers
First Published:First published in Extended abstracts of 1998 Sixth International Workshop on Computational Electronics (1998):58-61
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher

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