Monte Carlo investigation of optimal device architectures for SiGe FETs

Roy, S., Kaya, S., Babiker, S., Asenov, A. and Barker, J.R. (1998) Monte Carlo investigation of optimal device architectures for SiGe FETs. In: International Workshop on Computational Electronics, Osaka, Japan, 19-21 October 1998, pp. 210-213. ISBN 0780343697 (doi: 10.1109/IWCE.1998.742749)

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Publisher's URL: http://dx.doi.org/10.1109/IWCE.1998.742749

Abstract

Strained silicon channel FETs grown on virtual SiGe substrates show clear potential for RF applications, in a material system compatible with silicon VLSI. However, the optimisation of practical RF devices requires some care. 0.1-0.12 μm gate length designs are investigated using Monte Carlo techniques. Although structures based on III-V experience show fT values of up to 94 GHz, more realistic designs are shown to be limited by parallel conduction and ill constrained effective channel lengths. Aggressively scaled SiGe devices, following state-of-the-art CMOS technologies, show fT values of up to 80 GHz.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Asenov, Professor Asen and Roy, Professor Scott
Authors: Roy, S., Kaya, S., Babiker, S., Asenov, A., and Barker, J.R.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Device Modelling Group
Publisher:Institute of Electrical and Electronics Engineers
ISBN:0780343697
Copyright Holders:Copyright © 1998 Institute of Electrical and Electronics Engineers
First Published:First published in Extended abstracts of 1998 Sixth International Workshop on Computational Electronics (1998):210-213
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher

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