Integrated atomistic process and device simulation of decananometre MOSFETs

Asenov, A. , Jaraiz, M., Roy, S., Roy, G. and Adamu-Lema, F. (2002) Integrated atomistic process and device simulation of decananometre MOSFETs. In: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2002), Kobe, Japan, 4-6 Sep 2002, pp. 87-90. ISBN 4891140275 (doi:10.1109/SISPAD.2002.1034523)

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Publisher's URL: http://dx.doi.org/10.1109/SISPAD.2002.1034523

Abstract

In this paper we present a methodology for the integrated atomistic process and device simulation of decananometre MOSFETs. The atomistic process simulations were carried out using the kinetic Monte Carlo process simulator DADOS, which is now integrated into the Synopsys 3D process and device simulation suite Taurus. The device simulations were performed using the Glasgow 3D statistical atomistic simulator, which incorporates density gradient quantum corrections. The overall methodology is illustrated in the atomistic process and device simulation of a well behaved 35 nm physical gate length MOSFET reported by Toshiba.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Asenov, Professor Asen and Roy, Dr Gareth
Authors: Asenov, A., Jaraiz, M., Roy, S., Roy, G., and Adamu-Lema, F.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
College of Science and Engineering > School of Physics and Astronomy
Research Group:Device Modelling Group
Publisher:Institute of Electrical and Electronics Engineers
ISBN:4891140275
Copyright Holders:Copyright © 2002 Institute of Electrical and Electronics Engineers
First Published:First published in International Conference on Simulation of Semiconductor Processes and Devices(2002):87-90
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher

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