Gate tunnelling and impact ionisation in sub 100 nm PHEMTs

Kalna, K. and Asenov, A. (2002) Gate tunnelling and impact ionisation in sub 100 nm PHEMTs. In: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2002), Kobe, Japan, 4-6 September 2002, pp. 139-142. ISBN 4891140275 (doi: 10.1109/SISPAD.2002.1034536)

Abstract

Impact ionization and thermionic tunnelling as two possible breakdown mechanisms in scaled pseudomorphic high electron mobility transistors (PHEMTs) are investigated by Monte Carlo (MC) device simulations. Impact ionization is included in MC simulation as an additional scattering mechanism whereas thermionic tunnelling is treated in the WKB approximation during each time step in selfconsistent MC simulation. Thermionic tunnelling starts at very low drain voltages but then quickly saturates. Therefore, it should not drastically affect the performance of scaled devices. Impact ionization threshold occurs at greater drain voltages which should assure a reasonable operation voltage scale for all scaled PHEMTs.

• Item Type: Conference Proceedings
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Asenov, Professor Asen and Kalna, Dr Karol
• Authors: Kalna, K., and Asenov, A.
• Subjects: T Technology > TJ Mechanical engineering and machinery
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Research Group: Device Modelling Group
• Publisher: Institute of Electrical and Electronics Engineers
• ISBN: 4891140275
• Copyright Holders: Copyright © 2002 Institute of Electrical and Electronics Engineers
• First Published: First published in International Conference on Simulation of Semiconductor Processes and Devices(2002):139-142
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher