Scaling study of Si and strained Si n-MOSFETs with different high-k gate stacks

Yang, L., Watling, J. R., Adam-Lema, F., Asenov, A. and Barker, J. R. (2004) Scaling study of Si and strained Si n-MOSFETs with different high-k gate stacks. In: IEEE International Electron Devices Meeting, San Francisco, California, 13-15 December 2004, pp. 597-600. ISBN 0780386841 (doi: 10.1109/IEDM.2004.1419232)

Abstract

Using ensemble Monte Carlo device simulations, this paper studies the impact of interface roughness and soft-optical phonon scattering on the performance of sub-100nm Si and strained Si MOSFETs with different high-k gate stacks. Devices with gate lengths down to 25nm have been investigated.

• Item Type: Conference Proceedings
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Asenov, Professor Asen and Watling, Dr Jeremy
• Authors: Yang, L., Watling, J. R., Adam-Lema, F., Asenov, A., and Barker, J. R.
• Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Research Group: Device Modelling Group
• Publisher: Institute of Electrical and Electronics Engineers
• ISBN: 0780386841
• Copyright Holders: Copyright © 2004 Institute of Electrical and Electronics Engineers
• First Published: First published in IEEE International Electron Devices Meeting 2004 IEDM technical digest (2004):597-600
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher