Yang, L., Watling, J. R., Asenov, A., Barken, J. R. and Roy, S. (2004) Sub-100nm strained Si CMOS: device performance and circuit behavior. In: International Conference on Solid-State and Integrated Circuits Technology, Beijing, China, 18-21 October 2004, pp. 983-986. ISBN 078038511X (doi: 10.1109/ICSICT.2004.1436670)
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Publisher's URL: http://dx.doi.org/10.1109/ICSICT.2004.1436670
Abstract
Using comprehensive device simulations, performance enhancement of sub-100nm strained Si MOSFETs has been investigated. Circuit behavior of conventional Si, strained Si, conventional Si SOI and strained SOI ring oscillators has been assessed.
Item Type: | Conference Proceedings |
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Status: | Published |
Refereed: | Yes |
Glasgow Author(s) Enlighten ID: | Asenov, Professor Asen and Watling, Dr Jeremy and Roy, Professor Scott |
Authors: | Yang, L., Watling, J. R., Asenov, A., Barken, J. R., and Roy, S. |
Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
College/School: | College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering |
Research Group: | Device Modelling Group |
Publisher: | Institute of Electrical and Electronics Engineers |
ISBN: | 078038511X |
Copyright Holders: | Copyright © 2004 Institute of Electrical and Electronics Engineers |
First Published: | First published in International Conference on Solid-State and Integrated Circuits Technology proceedings (2004):983-986 |
Publisher Policy: | Reproduced in accordance with the copyright policy of the publisher |
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