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Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxide

Asenov, A., and Saini, S. (2000) Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxide. IEEE Transactions on Electron Devices, 47 (4). pp. 805-812. ISSN 0018-9383 (doi:10.1109/16.830997)

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Publisher's URL: http://dx.doi.org/10.1109/16.830997

Abstract

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3D) “atomistic” simulation technique. MOSFETs with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled to thickness in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect of the polysilicon grain boundaries on the threshold voltage variation are also presented.

Item Type:Article
Status:Published
Refereed:Yes
Glasgow Author(s):Asenov, Prof Asen
Authors: Asenov, A., and Saini, S.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Device Modelling Group
Journal Name:IEEE Transactions on Electron Devices
Publisher:Institute of Electrical and Electronics Engineers
ISSN:0018-9383
Copyright Holders:Copyright © 2000 Institute of Electrical and Electronics Engineers
First Published:First published in IEEE Transactions on Electron Devices 47(4):805-812
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher

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