SECDA: Efficient Hardware/Software Co-design of FPGA-based DNN Accelerators for Edge Inference

Haris, J., Gibson, P. , Cano, J. , Bohm Agostini, N. and Kaeli, D. (2021) SECDA: Efficient Hardware/Software Co-design of FPGA-based DNN Accelerators for Edge Inference. In: 2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Belo Horizonte, Brazil, 26-28 Oct 2021, pp. 33-43. ISBN 9781665443012 (doi: 10.1109/SBAC-PAD53543.2021.00015)

Abstract

Edge computing devices inherently face tight resource constraints, which is especially apparent when deploying Deep Neural Networks (DNN) with high memory and compute demands. FPGAs are commonly available in edge devices. Since these reconfigurable circuits can achieve higher throughput and lower power consumption than general purpose processors, they are especially well-suited for DNN acceleration. However, existing solutions for designing FPGA-based DNN accelerators for edge devices come with high development overheads, given the cost of repeated FPGA synthesis passes, reimplementation in a Hardware Description Language (HDL) of the simulated design, and accelerator system integration. In this paper we propose SECDA, a new hardware/software co-design methodology to reduce design time of optimized DNN inference accelerators on edge devices with FPGAs. SECDA combines cost-effective SystemC simulation with hardware execution, streamlining design space exploration and the development process via reduced design evaluation time. As a case study, we use SECDA to efficiently develop two different DNN accelerator designs on a PYNQ-Z1 board, a platform that includes an edge FPGA. We quickly and iteratively explore the system’s hardware/software stack, while identifying and mitigating performance bottlenecks. We evaluate the two accelerator designs with four common DNN models, achieving an average performance speedup across models of up to 3.5× with a 2.9× reduction in energy consumption over CPU-only inference.

• Item Type: Conference Proceedings
• Keywords: Accelerator design, design methodology, hardware-software co-design, SystemC, simulation, HLS.
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Cano Reyes, Dr Jose and Gibson, Mr Perry and Haris, Jude
• Authors: Haris, J., Gibson, P., Cano, J., Bohm Agostini, N., and Kaeli, D.
• College/School: College of Science and Engineering > School of Computing Science
• ISSN: 2643-3001
• ISBN: 9781665443012
• Copyright Holders: Copyright © 2021 IEEE
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher

Project Code	Award No	Project Name	Principal Investigator	Funder's Name	Funder Ref	Lead Dept
305200		DTP 2018-19 University of Glasgow	Mary Beth Kneafsey	Engineering and Physical Sciences Research Council (EPSRC)	EP/R513222/1	MVLS - Graduate School