Vmin Prediction for Negative Capacitance MOSFET based SRAM

Dutta, T. , Georgiev, V. and Asenov, A. (2020) Vmin Prediction for Negative Capacitance MOSFET based SRAM. In: 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 01-30 Sep 2020, ISBN 9781728187655 (doi:10.1109/EUROSOI-ULIS49407.2020.9365282)

[img] Text
236451.pdf - Accepted Version

1MB

Abstract

In this work we show that SRAM cells designed using negative capacitance (NC) based MOSFETs (NCFETs) can offer improved Vmin (minimum supply voltage needed for reliable operation) compared to conventional MOSFET based SRAM. Increased noise margins and reduced variability in NCFETs lead to this lowering of Vmin. For this work we use a modified version of the standard BSIM4 compact model for bulk MOSFETs by coupling it with the Landau-Khalatnikov model of ferroelectrics in a self-consistent manner, while the statistical variability information of the reference device is extracted from 3D statistical TCAD simulations.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Asenov, Professor Asen and Dutta, Dr Tapas and Georgiev, Dr Vihar
Authors: Dutta, T., Georgiev, V., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Device Modeling Group
ISSN:2472-9132
ISBN:9781728187655
Published Online:09 March 2021
Copyright Holders:Copyright © 2020 IEEE
First Published:First published in 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
Publisher Policy:Reproduced in accordance with the publisher copyright policy
Related URLs:

University Staff: Request a correction | Enlighten Editors: Update this record