Interplay of RDF and Gate LER Induced Statistical Variability in Negative Capacitance FETs

Dutta, T. , Georgiev, V. and Asenov, A. (2018) Interplay of RDF and Gate LER Induced Statistical Variability in Negative Capacitance FETs. In: 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Austin, Texas, USA, 24-26 Sept. 2018, pp. 262-265. ISBN 9781538667903 (doi:10.1109/SISPAD.2018.8551710)

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Abstract

The downscaling of traditional DRAM [1] is facing challenges due to the presence of external capacitor. Z2FET [2-5] has been demonstrated as a promising DRAM candidate eliminating the need for external capacitor. In the past, attention was focused on the optimization of device structure [5] and fabrication process [2] without paying much attention to the Statistical (local) Variability (SV) which is crucial for any memory technology. In this paper, a novel simulation methodology is proposed and the SV of DRAM Memory Window (MW) is investigated systematically. It is found that SV of MW is dominated by Metal Gate Granularity (MGG) coming from the Gated-SOI region of the Z2FET. Although Random Discrete Dopant (RDD) induced variations in the threshold voltage (Vth) has larger spread in the Intrinsic-SOI part, it has no significant effect on the overall Z2FET characteristics. Based on the proposed methodology, SV of MW at different process corners has also been studied. Results reveal the necessity for further process optimization due to the best corner giving rise not only to larger average MW but also less variations. Furthermore, circuit level read performance (including the variability) of a Z2FET-based memory cell have been evaluated. All these findings could guide the further performance optimization from both device and memory cell circuit point of view for Z2FET-based volatile memory product development.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Asenov, Professor Asen and Dutta, Dr Tapas and Georgiev, Dr Vihar
Authors: Dutta, T., Georgiev, V., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Device Modeling Group
ISSN:1946-1577
ISBN:9781538667903
Copyright Holders:Copyright © 2018 IEEE
First Published:First published in 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
Publisher Policy:Reproduced in accordance with the publisher copyright policy

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
172266REMINDERAsen AsenovEuropean Commission (EC)687931ENG - Electronics & Nanoscale Engineering