FPGA-based Built-in Testbed for Command Interpretations and Computational Load Distribution

Cao, Q. and Lim, M. H. (2009) FPGA-based Built-in Testbed for Command Interpretations and Computational Load Distribution. In: 2009 12th International Symposium on Integrated Circuits, Singapore, Singapore, 14-16 Dec 2009, pp. 643-646. ISBN 9789810824686

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Publisher's URL: https://ieeexplore.ieee.org/document/5403688


A testbed with built-in data processing capability is presented in this paper. The built-in testbed is designed for a small form factor storage protocol. In the market, there are several dedicated test equipments supporting the protocol of the storage device. However, they are more suitable in the development stage. A built-in testbed which is suitable for both the development stage and production stage will benefit the industry. The most computing power relies on a FPGA, which is with high processing throughput. It releases the test host from the heavy computational load. It makes the dedicated test equipments to be unnecessary, which is eventually replaced by a normal person computer (PC). The hardware architecture of the proposed testbed is described in detail in this paper.

Item Type:Conference Proceedings
Glasgow Author(s) Enlighten ID:Cao, Dr Qi
Authors: Cao, Q., and Lim, M. H.
College/School:College of Science and Engineering > School of Computing Science
Published Online:02 February 2010

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