Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs

Nabi, S. W. and Vanderbauwhede, W. (2019) Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs. In: 33rd IEEE International Parallel and Distributed Processing Symposium, Reconfigurable Architectures Workshop (RAW 2019), Rio de Janeiro, Brazil, 20-24 May 2019, ISBN 9781728135106 (doi:10.1109/IPDPSW.2019.00024)

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Abstract

A key requirement for high performance on FPGAs is to maintain continuous data streaming from the DRAM. An impediment in many computations, especially in the scientific computing domain, is irregular stencils and boundary conditions, requiring memory accesses that are random, redundant, or both. To address this problem, we present Smache, a novel smart-caching framework that uses FPGA on-chip memory resources for optimising access for arbitrary stencil shapes and boundary conditions. We propose a combination of stream and static buffers, and it is the latter that allows arbitrarily large offsets in stencils. The architecture is complemented by a formal model for determining buffer configuration. We propose a hybrid use of the block and distributed RAM on the FPGA. The design is validated for a 2D grid, 4-point stencil with circular boundaries.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Nabi, Dr Syed Waqar and Vanderbauwhede, Professor Wim
Authors: Nabi, S. W., and Vanderbauwhede, W.
College/School:College of Science and Engineering > School of Computing Science
ISBN:9781728135106
Copyright Holders:Copyright © 2019 IEEE
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher
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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
614451Exploiting Parallelism through Type Transformations for Hybrid Manycore Systems.Wim VanderbauwhedeEngineering and Physical Sciences Research Council (EPSRC)EP/L00058X/1COM - COMPUTING SCIENCE