Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs

Nabi, S. W. and Vanderbauwhede, W. (2019) Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs. In: 33rd IEEE International Parallel and Distributed Processing Symposium, Reconfigurable Architectures Workshop (RAW 2019), Rio de Janeiro, Brazil, 20-24 May 2019, (Accepted for Publication)

Nabi, S. W. and Vanderbauwhede, W. (2019) Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs. In: 33rd IEEE International Parallel and Distributed Processing Symposium, Reconfigurable Architectures Workshop (RAW 2019), Rio de Janeiro, Brazil, 20-24 May 2019, (Accepted for Publication)

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Item Type:Conference Proceedings
Status:Accepted for Publication
Refereed:Yes
Glasgow Author(s) Enlighten ID:Vanderbauwhede, Dr Wim and Nabi, Dr Syed Waqar
Authors: Nabi, S. W., and Vanderbauwhede, W.
College/School:College of Science and Engineering > School of Computing Science
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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
614451Exploiting Parallelism through Type Transformations for Hybrid Manycore Systems.Wim VanderbauwhedeEngineering and Physical Sciences Research Council (EPSRC)EP/L00058X/1COM - COMPUTING SCIENCE