Plana, L. A., Furber, S. B., Temple, S., Khan, M., Shi, Y., Wu, J. and Yang, S. (2007) A GALS infrastructure for a massively parallel multiprocessor. IEEE Design and Test of Computers, 24(5), pp. 454-463. (doi: 10.1109/MDT.2007.149)
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Abstract
This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons. Every node of the design comprises 20 ARM9 cores, a memory interface, a multicast router, and two NoC structures for communicating between internal cores and the environment. The NoCs are asynchronous; the cores and RAM interfaces are synchronous. This GALS approach decouples clocking concerns for different parts of the die, leading to greater power efficiency.
| Item Type: | Articles |
|---|---|
| Additional Information: | The Spinnaker project is supported by the Engineering and Physical Sciences Research Council, partly through the Advanced Processor Technologies Portfolio Partnership at the University of Manchester, and also by ARM and Silistix. Steve Furber holds a Royal Society-Wolfson Research Merit Award. |
| Status: | Published |
| Refereed: | Yes |
| Glasgow Author(s) Enlighten ID: | Yang, Dr Shufan |
| Authors: | Plana, L. A., Furber, S. B., Temple, S., Khan, M., Shi, Y., Wu, J., and Yang, S. |
| College/School: | College of Science and Engineering > School of Engineering > Systems Power and Energy |
| Journal Name: | IEEE Design and Test of Computers |
| Publisher: | IEEE |
| ISSN: | 0740-7475 |
| ISSN (Online): | 1558-1918 |
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