A Bit Cycling Method for Improving the DNL/INL in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)

Fan, H., Wang, C., Xiong, H., Feng, Q., Li, D., Zhang, K., Diao, X., Lin, L. and Heidari, H. (2018) A Bit Cycling Method for Improving the DNL/INL in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). In: 2018 New Generation of CAS (NGCAS), Valletta, Malta, 20-23 Nov 2018, ISBN 9781538676813 (doi:10.1109/NGCAS.2018.8572141)

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Abstract

This paper presents a bit cycling method to improve the max root mean square (rms) value of differential nonlinearity (DNL) and the max rms value of integral nonlinearity (INL) for successive approximation register (SAR) analog-to-digital converter (ADC). Neither an additional DAC nor any complex correction algorithm are needed in this work, it is only necessary to switch between two different bit cycling modes, then it is possible to avoid the accumulation error of the capacitor mismatch caused by the same codes, so as to achieve the purpose of upgrading DNL and INL, and finally to improve the static linearity of SAR ADC.

Item Type:Conference Proceedings
Additional Information:The work of Hua Fan was supported by the National Natural Science Foundation of China (NSFC) under Grant 61771111 and 61401066, as well as supported by China Postdoctoral Science Foundation under grant 2017M612940. The work of Quanyuan Feng was supported by the National Natural Science Foundation of China (NSFC) under Grant 61531016, supported by the project of Science and Technology Support Program of Sichuan Province under Grant 2018GZ0139, and in part by the Sichuan Provincial Science and Technology Important Projects under Grant 2017GZ0110.
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Heidari, Dr Hadi
Authors: Fan, H., Wang, C., Xiong, H., Feng, Q., Li, D., Zhang, K., Diao, X., Lin, L., and Heidari, H.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
ISBN:9781538676813

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