Quantum Transport Investigation of Threshold Voltage Variability in Sub-10 nm JunctionlessSi Nanowire FETs

Berrada, S., Lee, J., Carrillo-Nunez, H., Medina Bailon, C., Adamu-Lema, F., Georgiev, V. and Asenov, A. (2018) Quantum Transport Investigation of Threshold Voltage Variability in Sub-10 nm JunctionlessSi Nanowire FETs. In: 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Austin, TX, 24-26 Sept 2018, pp. 244-247. ISBN 9781538667910 (doi:10.1109/SISPAD.2018.8551638)

Berrada, S., Lee, J., Carrillo-Nunez, H., Medina Bailon, C., Adamu-Lema, F., Georgiev, V. and Asenov, A. (2018) Quantum Transport Investigation of Threshold Voltage Variability in Sub-10 nm JunctionlessSi Nanowire FETs. In: 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Austin, TX, 24-26 Sept 2018, pp. 244-247. ISBN 9781538667910 (doi:10.1109/SISPAD.2018.8551638)

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Abstract

In this paper, we use the Non-Equilibrium Green's Function formalism to study the dependence of the threshold voltage variability on the cross-section shape and the gate length in Junction Less Field Effect Transistors. Each configuration, i.e. gate length and cross-section, was investigated using a statistical ensemble of 100 samples. We found that the variability in threshold voltage is increased independently of the cross-section shape when the gate length isshrunk down to 5 nm. We attribute this results to the higher wave function “randomization” in longer gate lengths.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Carrillo-Nunez, Dr Hamilton and Lee, Jaehyun and Georgiev, Dr Vihar and Asenov, Professor Asen and Medina Bailon, Miss Cristina and Berrada, Dr Salim and Adamu-Lema, Dr Fikru
Authors: Berrada, S., Lee, J., Carrillo-Nunez, H., Medina Bailon, C., Adamu-Lema, F., Georgiev, V., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
ISBN:9781538667910
Copyright Holders:Copyright © 2018 IEEE
First Published:First published in Proceedings of 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 244-247
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
703701SUPERAID7Asen AsenovEuropean Commission (EC)688101ENG - ENGINEERING ELECTRONICS & NANO ENG