HW/SW Co-designed Processors: Challenges, Design Choices and a Simulation Infrastructure for Evaluation

Kumar, R., Cano, J. , Pavlou, D., Stavrou, K., Gibert, E., Martinez, A. and González, A. (2017) HW/SW Co-designed Processors: Challenges, Design Choices and a Simulation Infrastructure for Evaluation. In: 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Santa Rosa, CA, USA, 24-25 Apr 2017, pp. 185-194. ISBN 9781538638903 (doi:10.1109/ISPASS.2017.7975290)

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Abstract

Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. Therefore, researchers have been looking at unconventional architectures to boost single thread performance without running into the power wall. HW/SW co-designed processors like Nvidia Denver, are emerging as a promising alternative. However, HW/SW co-designed processors need to address some key challenges such as startup delay, providing high performance with simple hardware, translation/optimization overhead, etc. before they can become mainstream. A fundamental requirement for evaluating different design choices and trade-offs to meet these challenges is to have a simulation infrastructure. Unfortunately, there is no such infrastructure available today. Building the aforementioned infrastructure itself poses significant challenges as it encompasses the complexities of not only an architectural framework but also of a compilation one. This paper identifies the key challenges that HW/SW codesigned processors face and the basic requirements for a simulation infrastructure targeting these architectures. Furthermore, the paper presents DARCO, a simulation infrastructure to enable research in this domain.

Item Type:Conference Proceedings
Additional Information:This work was supported by the Spanish State Research Agency under grants TIN2013-44375-R and TIN2016-75344-R (AEI/FEDER, EU).
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Cano Reyes, Dr Jose
Authors: Kumar, R., Cano, J., Pavlou, D., Stavrou, K., Gibert, E., Martinez, A., and González, A.
College/School:College of Science and Engineering > School of Computing Science
ISBN:9781538638903
Published Online:13 July 2017
Copyright Holders:Copyright © 2017 IEEE
First Published:First published in 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS): 185-194
Publisher Policy:Reproduced in accordance with the publisher copyright policy

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