High Aspect Ratio Junctionless InGaAs FinFETs Fabricated Using a Top-Down Approach

Millar, D.A.J., Li, X. , Peralagu, U. , Steer, M.J., Pavey, I.M., Gaspar, G., Schmidt, M., Hurley, P.K. and Thayne, I.G. (2018) High Aspect Ratio Junctionless InGaAs FinFETs Fabricated Using a Top-Down Approach. 2018 76th Device Research Conference (DRC), Santa Barbara, CA, USA, 24-27 Jun 2018. ISBN 9781538630280 (doi:10.1109/DRC.2018.8442150)

Millar, D.A.J., Li, X. , Peralagu, U. , Steer, M.J., Pavey, I.M., Gaspar, G., Schmidt, M., Hurley, P.K. and Thayne, I.G. (2018) High Aspect Ratio Junctionless InGaAs FinFETs Fabricated Using a Top-Down Approach. 2018 76th Device Research Conference (DRC), Santa Barbara, CA, USA, 24-27 Jun 2018. ISBN 9781538630280 (doi:10.1109/DRC.2018.8442150)

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Abstract

The junctionless MOSFET (JLFET) architecture has attracted much attention as an enabling technology for ultra-scaled CMOS devices [1]. The dominant scattering mechanism in JLFETs is impurity scattering due to its necessarily highly doped channel [1]. Accordingly, III-V's may offer an even greater advantage as the channel material for JLFETs than for conventional MOSFETs as they suffer less from mobility degradation due to impurity scattering [2]. Current Si CMOS devices employ non-planar architectures with high aspect ratio fins which serve to increase the on current (Ion) per chip surface area [3]. This necessitates that any incarnation of a III - V MOSFET must also exploit the vertical dimension. Additionally, it must do so by employing a ‘top-down’ fabrication approach to remain compatible with Si CMOS processing. This requires a low Dit dielectric interface to etched III-V fin sidewalls. To date, all III-V junctionless FinFETs (JLFinFETs) demonstrated have employed fin heights which are smaller than the maximum depletion width of their respective channels, and therefore can be well modulated by the top gate only: offering little insight into the effectiveness of the gated sidewalls. We implement a low damage etch process to form high aspect ratio, In053Ga047As JLFinFETs which have record performance in terms of Ion normalized to fin width.

Item Type:Conference or Workshop Item
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Thayne, Professor Iain and Peralagu, Mr Uthayasankaran and Steer, Dr Matthew and Li, Dr Xu and Millar, Mr David
Authors: Millar, D.A.J., Li, X., Peralagu, U., Steer, M.J., Pavey, I.M., Gaspar, G., Schmidt, M., Hurley, P.K., and Thayne, I.G.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
ISBN:9781538630280
Published Online:23 August 2018
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