Extended analysis of the Z²-FET: operation as capacitorless eDRAM

Navarro, C. et al. (2017) Extended analysis of the Z²-FET: operation as capacitorless eDRAM. IEEE Transactions on Electron Devices, 64(11), pp. 4486-4491. (doi: 10.1109/TED.2017.2751141)

Abstract

The Z²-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulatordevices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier’s diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z²-FET’s memory state is not exclusively defined by the inner charge but also by the reading conditions.

• Item Type: Articles
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Asenov, Professor Asen and Duan, Dr Meng and Cheng, Dr Binjie
• Authors: Navarro, C., Lacord, J., Parihar, M. S., Adamu-Lema, F., Duan, M., Rodriguez, N., Cheng, B., El Dirani, H., Barbe, J.-C., Fonteneau, P., Bawedin, M., Millar, C., Galy, P., Le Royer, C., Karg, S., Wells, P., Kim, Y.-T., Asenov, A., Cristoloveanu, S., and Gamiz, F.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Journal Name: IEEE Transactions on Electron Devices
• Publisher: IEEE
• ISSN: 0018-9383
• ISSN (Online): 1557-9646
• Published Online: 20 September 2017
• Copyright Holders: Copyright © 2017 IEEE
• First Published: First published in IEEE Transactions on Electron Devices 64(11):4486-4491
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher