Statistical Variability in 5 nm Vertically Stacked Lateral Si Nanowire Transistors

Al-Ameri, T. (2017) Statistical Variability in 5 nm Vertically Stacked Lateral Si Nanowire Transistors. In: 12th IEEE Nanotechnology Materials and Devices Conference (NMDC 2017), Singapore, 2-4 Oct 2017, (Accepted for Publication)

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Abstract

In this work, we present a comprehensive computational study of the impact of the principle sources of statistical variability, i.e., random dopant fluctuations, wire edge roughness, and metal gate granularity, on the threshold voltage, drain-induced barrier lowering, and drive current. Furthermore, we investigated the position dependent performance and geometrical variation of the lateral nanowires in the stack as new sources of process variability.

Item Type:Conference Proceedings
Status:Accepted for Publication
Refereed:Yes
Glasgow Author(s) Enlighten ID:Al-Ameri, Talib Mahmood Ali
Authors: Al-Ameri, T.
College/School:College of Science and Engineering > School of Engineering
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