Variability-Aware Simulations of 5 nm Vertically Stacked Lateral Si Nanowires Transistors

Al-Ameri, T. , Georgiev, V.P. , Adamu-Lema, F. and Asenov, A. (2017) Variability-Aware Simulations of 5 nm Vertically Stacked Lateral Si Nanowires Transistors. International Workshop on Computational Nanotechnology, Windermere, UK, 5-9 June 2017.

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Abstract

In this work, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs) considering various sources of statistical variability. Our simulation approach is based on various simulations techniques to capture the complexity in such ultra-scaled device.

Item Type:Conference or Workshop Item
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Asenov, Professor Asen and Al-Ameri, Talib Mahmood Ali and Adamu-Lema, Dr Fikru and Georgiev, Dr Vihar
Authors: Al-Ameri, T., Georgiev, V.P., Adamu-Lema, F., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Copyright Holders:Copyright © 2017 The Authors
Publisher Policy:Reproduced with the permission of the Authors
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