Thin hybrid pixel assembly with backside compensation layer on ROIC

Bates, R. et al. (2017) Thin hybrid pixel assembly with backside compensation layer on ROIC. Journal of Instrumentation, 12(1), C01018. (doi: 10.1088/1748-0221/12/01/C01018)

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The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m2. For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of −175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.

Item Type:Articles
Additional Information:This work was supported by the U.K. Science and Technology Facilities Council, STFC.
Glasgow Author(s) Enlighten ID:Ashby, Mr Joe and Mcmullen, Mr Thomas and Gray, Chloe and Bates, Dr Richard and Doherty, Mr Frederick and Cunningham, Dr Liam and Buttar, Professor Craig
Authors: Bates, R., Buttar, C., McMullen, T., Cunningham, L., Ashby, J., Doherty, F., Gray, C., Pares, G., Vignoud, L., Kholti, B., and Vahanen, S.
College/School:College of Science and Engineering > School of Physics and Astronomy
Journal Name:Journal of Instrumentation
Publisher:IOP Publishing
ISSN (Online):1748-0221
Published Online:05 January 2017

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