Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications

Al-Ameri, T. , Georgiev, V.P. , Adamu-Lema, F. and Asenov, A. (2017) Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications. IEEE Journal of the Electron Devices Society, 5(6), pp. 466-472. (doi: 10.1109/JEDS.2017.2752465)

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Abstract

In this paper we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson-Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this work.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Georgiev, Dr Vihar and Asenov, Professor Asen and Al-Ameri, Talib Mahmood Ali and Adamu-Lema, Dr Fikru
Authors: Al-Ameri, T., Georgiev, V.P., Adamu-Lema, F., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering
College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Journal of the Electron Devices Society
Publisher:IEEE
ISSN:2168-6734
ISSN (Online):2168-6734
Published Online:19 September 2017
Copyright Holders:Copyright © 2017 The Authors
First Published:First published in IEEE Journal of the Electron Devices Society 5(6):466-472
Publisher Policy:Reproduced under a Creative Commons License

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
730291Quantum Electronics Device Modelling (QUANTDEVMOD)Vihar GeorgievEngineering and Physical Sciences Research Council (EPSRC)EP/P009972/1ENG - ENGINEERING ELECTRONICS & NANO ENG
703701SUPERAID7Asen AsenovEuropean Commission (EC)688101ENG - ENGINEERING ELECTRONICS & NANO ENG