Capacitive Multiplier for Timing Generation

National Semiconductor Corporation (1999) Capacitive Multiplier for Timing Generation. .

Abstract

A capacitive multiplier circuit for an integrated circuit includes a capacitor coupled between a first node and a second node. A current source is coupled to provide a controlling current to the second node. A first current path shunts the first node and a second current path shunts the second node. The first current path is a first transistor having its conductance path connected between the first node and the substrate and its control electrode connected to the first node. The second current path is a second transistor having its conductance path connected between the second node and the substrate and its control electrode connected to the first node. The current ratio between the two current paths will be determined by the relative areas of the respective conductance paths.

• Item Type: Patents
• Additional Information: Application Number US 08/764,524; ; Publication Number US5900771 A; ; Inventor: Duncan J. Bremner.
• Status: Published
• Glasgow Author(s) Enlighten ID: Bremner, Dr Duncan
• Authors: Bremner, D.
• College/School: College of Science and Engineering > School of Engineering