Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture

Brown, A.R., Roy, G. and Asenov, A. (2007) Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture. IEEE Transactions on Electron Devices, 54(11), pp. 3056-3063. (doi: 10.1109/TED.2007.907802)

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Abstract

In this paper, we present a comprehensive statistical 3-D simulation study of the effect of polysilicon (poly-Si) gate granularity on the threshold voltage variability in decananometer MOSFETs with conventional (bulk) architecture. Initially, the effect of both the pinning of the Fermi level and the doping nonuniformity at the poly-Si grain boundaries are studied and compared considering a single grain boundary crossing through the middle of the channel for different pinning positions and doping concentrations at the boundary. This is followed by systematic simulation results for the impact of the grain-size distribution on the standard deviation of the threshold voltage in a simple 30 30 nm MOSFET with uniform channel doping for different pinning positions and doping levels at the grain boundaries. Finally, simulation results for the magnitude of the threshold voltage variations induced by the poly-Si granularity are presented for a set of carefully scaled ldquorealisticrdquo bulk MOSFETs with gate lengths of 35, 25, 18, 13, and 9 nm and are compared with the variations introduced by random discrete dopants and line-edge roughness.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Asenov, Professor Asen and Brown, Mr Andrew and Roy, Dr Gareth
Authors: Brown, A.R., Roy, G., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
College of Science and Engineering > School of Physics and Astronomy
Journal Name:IEEE Transactions on Electron Devices
Publisher:IEEE
ISSN:0018-9383
ISSN (Online):1557-9646

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
368421Meeting the materials challenges of nano-CMOS electronicsAsen AsenovEngineering & Physical Sciences Research Council (EPSRC)GR/S80097/01Electronic and Nanoscale Engineering