Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications

Seo, J., Lee, J. and Shin, M. (2017) Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications. IEEE Transactions on Electron Devices, 64(4), pp. 1793-1798. (doi: 10.1109/TED.2017.2658673)

Abstract

We investigate the performance of hysteresis-free short-channel negative-capacitance FETs (NCFETs) by combining quantum-mechanical calculations with the Landau-Khalatnikov equation. When the subthreshold swing (SS) becomes smaller than 60 mV/dec, a negative value of drain-induced barrier lowering is obtained. This behavior, drain-induced barrier rising (DIBR), causes negative differential resistance in the output characteristics of the NCFETs. We also examine the performance of an inverter composed of hysteresis-free NCFETs to assess the effects of DIBR at the circuit level. Contrary to our expectation, although hysteresis-free NCFETs are used, hysteresis behavior is observed in the transfer properties of the inverter. Furthermore, it is expected that the NCFET inverter with hysteresis behavior can be used as a Schmitt trigger inverter.

• Item Type: Articles
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Lee, Mr Jaehyun
• Authors: Seo, J., Lee, J., and Shin, M.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Journal Name: IEEE Transactions on Electron Devices
• Publisher: Institute of Electrical and Electronics Engineers
• ISSN: 0018-9383
• ISSN (Online): 1557-9646
• Published Online: 14 February 2017
• Copyright Holders: Copyright © 2017 IEEE
• First Published: First published in IEEE Transactions on Electron Devices 64(4):1793-1798
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher