Resource Efficient Parallel Architectures for Linear Matrix Algebra in Real Time Adaptive Control Algorithms on Reconfigurable Logic

Khan, F. A., Ashraf, R. A., Abbasi, Q. H. and Nasir, A. A. (2008) Resource Efficient Parallel Architectures for Linear Matrix Algebra in Real Time Adaptive Control Algorithms on Reconfigurable Logic. In: 2008 Second International Conference on Electrical Engineering, Lahore, Pakistan, 25-26 Mar 2008, ISBN 9781424422920 (doi: 10.1109/ICEE.2008.4553939)

Abstract

Parallel and systolic structures for matrix algebra algorithms have been around for quite a long time. Various implementations of different numerical techniques exist. With the advent of reconfigurable logic, especially FPGAs, a need has arisen to revisit these architectures and produce resource efficient versions of these algorithms. We have produced resource efficient parallel architectures for LU Decomposition and Triangular Matrix Inversion, keeping in view data computational rate requirements for real time control systems. These architectures decrease memory logic resources considerably and also maintain excellent clock period results. They also have the capability to be mapped over each other thereby further reducing resource usage and also providing us with the additional facility of Matrix Multiplication.

• Item Type: Conference Proceedings
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Abbasi, Professor Qammer
• Authors: Khan, F. A., Ashraf, R. A., Abbasi, Q. H., and Nasir, A. A.
• College/School: College of Science and Engineering > School of Engineering
• ISBN: 9781424422920