Shortest path routing algorithm for hierarchical interconnection network-on-chip

Inam, O., Al Khanjari, S. and Vanderbauwhede, W. (2015) Shortest path routing algorithm for hierarchical interconnection network-on-chip. Procedia Computer Science, 56, pp. 409-414. (doi: 10.1016/j.procs.2015.07.228)

[img]
Preview
Text
137274.pdf - Published Version
Available under License Creative Commons Attribution Non-commercial No Derivatives.

1MB

Abstract

Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k-1) time where k=logn4-2 and k>0, in worst case to determine the next node along the shortest path.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Al Khanjari, Sharifa Abdullah Salim and Vanderbauwhede, Professor Wim and Inam, Mr Omair
Authors: Inam, O., Al Khanjari, S., and Vanderbauwhede, W.
College/School:College of Science and Engineering > School of Computing Science
Journal Name:Procedia Computer Science
Publisher:Elsevier
ISSN:1877-0509
Published Online:31 July 2015
Copyright Holders:Copyright © 2015 The Authors
First Published:First published in Procedia Computer Science 56: 409-414
Publisher Policy:Reproduced under a Creative Commons License

University Staff: Request a correction | Enlighten Editors: Update this record