Modeling of CMOS devices and circuits on flexible ultrathin chips

Vilouras, A. , Heidari, H. , Gupta, S. and Dahiya, R. (2017) Modeling of CMOS devices and circuits on flexible ultrathin chips. IEEE Transactions on Electron Devices, 64(5), pp. 2038-2046. (doi: 10.1109/TED.2017.2668899)

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The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-μm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20 μm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch).

Item Type:Articles
Glasgow Author(s) Enlighten ID:Vilouras, Anastasios and Heidari, Dr Hadi and Dahiya, Professor Ravinder and Gupta, Mr Shoubhik
Authors: Vilouras, A., Heidari, H., Gupta, S., and Dahiya, R.
College/School:College of Science and Engineering > School of Engineering
College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Transactions on Electron Devices
Publisher:Institute of Electrical and Electronics Engineers
ISSN (Online):1557-9646
Published Online:23 February 2017
Copyright Holders:Copyright © 2017 The Authors
First Published:First published in IEEE Transactions on Electron Devices 64(5): 2038-2046
Publisher Policy:Reproduced under a Creative Commons License

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
663861Engineering Fellowships for Growth: Printed Tactile SKINRavinder DahiyaEngineering & Physical Sciences Research Council (EPSRC)EP/M002527/1ENG - ENGINEERING ELECTRONICS & NANO ENG
659051Flexible Electronics Device Modelling (FLEXELDEMO)Ravinder DahiyaEngineering & Physical Sciences Research Council (EPSRC)EP/M002519/1ENG - ENGINEERING ELECTRONICS & NANO ENG
636381EPSRC Centre for Doctoral Training in Sensing and MeasurementAndrew HarveyEngineering & Physical Sciences Research Council (EPSRC)EP/L016753/1SCHOOL OF PHYSICS & ASTRONOMY