Silicon Transistors in Reduced Dimensions

Schupp, F., Mirza, M. M.A. , MacLaren, D. , Briggs, A., Paul, D. and Mol, J. (2017) Silicon Transistors in Reduced Dimensions. American Physical Society (APS) March Meeting, New Orleans, LA, USA, 13-17 Mar 2017.

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Junction-less nanowire transistors are being investigated for deeply scaled CMOS technology. To date almost all simulations to optimise the technology have been based on 3D or 2D modelling schemes. Here we will present measurements that unambiguously demonstrate 1D transport in sub-10 nm junction-less nanowires. The 1D nature of our device allows for excellent gate modulation despite doping concentrations being well above the metal-insulator transition. We find subthreshold slopes of 66 mV/dec, on- to off-current ratios above 108 and on-currents of 1.15 mA/µm for a gate overdrive of 1.0 V from transistors with a gate-length of 150 nm at room temperature. We observe Universal Conductance Scaling as a function of voltage and temperature similar to previous reports of transport in 1D systems. In low temperature transport experiments Quantum interference effects including signatures of subband filling are observed. We extract a phase coherence length of 15.7 nm from universal conductance fluctuations, suggesting possible ballistic transport in shorter channels. Our experiments demonstrate the importance of dimensionality in ultra-scaled CMOS devices and highlight the need for 1D device modelling schemes.

Item Type:Conference or Workshop Item
Glasgow Author(s) Enlighten ID:Mirza, Dr Muhammad M A and Paul, Professor Douglas and MacLaren, Dr Donald
Authors: Schupp, F., Mirza, M. M.A., MacLaren, D., Briggs, A., Paul, D., and Mol, J.
Subjects:Q Science > QC Physics
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
College of Science and Engineering > School of Physics and Astronomy

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