Georgiev, V. P. , Mirza, M. M. , Dochioiu, A.-I., Lema, F.-A., Amoroso, S. M., Towie, E., Riddet, C., MacLaren, D. A. , Asenov, A. and Paul, D. J. (2017) Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels. IEEE Transactions on Nanotechnology, 16(5), pp. 727-735. (doi: 10.1109/TNANO.2017.2665691)
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Abstract
The experimental results from 8 nm diameter silicon nanowire junctionless field effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/m for 1.0 V and 2.52 mA/m for 1.8 V gate overdrive with an off-current set at 100 nA/m. On- to off-current ratios above 108 with a subthreshold slope of 66 mV/dec are demonstrated at 25 oC. Simulations using drift-diffusion which include densitygradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength.
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