Si Nanowires and their Transistor Properties

Paul, D. , Mirza, M. M.A. and MacLaren, D. (2016) Si Nanowires and their Transistor Properties. EMN Meeting on Nanowires, Amsterdam, Netherlands, 16-19 May 2016.

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Si nanowires have a multitude of potential applications including transistors, memories, photovoltaics, thermoelectrics and qubits. For 10 nm scaled transistors, planar gate geometries due not provide sufficient electrostatic control of the channel and so nanowires have been suggested as a solution. Here we demonstrate a gate wrap-around metal-oxide semiconductor field effect transistor (MOSFET) using a Si nanowire as the channel. The devices were fabricated using top down electron-beam lithography, low damage dry etch, thermal oxidation and Al based metal. Transmission electron microscope images indicate a nanowire width of 8.0 ± 0.5 nm with a gate oxide of 16 nm. 150 nm gate length devices demonstrate excellent electrostatic control of the channel with Ion to Ioff ratios above 108, minimum subthreshold slopes of 66 mV/dec and Ion up to 35 μA/nanowire (4.4 mA/μm gate width) at VD = Vg = 1.5 V.

Item Type:Conference or Workshop Item
Glasgow Author(s) Enlighten ID:Mirza, Dr Muhammad M A and MacLaren, Dr Donald and Paul, Professor Douglas
Authors: Paul, D., Mirza, M. M.A., and MacLaren, D.
Subjects:Q Science > QC Physics
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
College of Science and Engineering > School of Physics and Astronomy
Research Group:Semiconductor Device Group and James Watt Nanofabrication Centre
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