Performance of Vertically Stacked Horizontal Si Nanowires Transistors: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study

Al-Ameri, T. , Georgiev, V.P. , Lema, A., Sadi, T., Towie, E., Riddet, C., Alexander, C. and Asenov, A. (2016) Performance of Vertically Stacked Horizontal Si Nanowires Transistors: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study. In: 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), Toulouse, France, 9-12 Oct 2016, ISBN 9781509043521 (doi:10.1109/NMDC.2016.7777117)

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Abstract

In this paper we present a simulation study of 5nm vertically stacked lateral nanowires transistor (NWTs). The study is based on calibration of drift-diffusion results against a Poisson-Schrodinger simulations for density-gradient quantum corrections, and against ensemble Monte Carlo simulations to calibrate carrier transport. As a result of these calibrated results, we have established a link between channel strain and the device performance. Additionally, we have compared the current flow in a single, double and triple vertically stacked lateral NWTs.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Towie, Dr Ewan and Sadi, Dr Toufik and Georgiev, Dr Vihar and Asenov, Professor Asen and Al-Ameri, Talib Mahmood Ali and Riddet, Mr Craig
Authors: Al-Ameri, T., Georgiev, V.P., Lema, A., Sadi, T., Towie, E., Riddet, C., Alexander, C., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
ISBN:9781509043521
Copyright Holders:Copyright © 2016 IEEE
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher

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