Optimising Simulation Data Structures for the Xeon Phi

Chimeh, M. K. and Cockshott, P. (2016) Optimising Simulation Data Structures for the Xeon Phi. In: 2016 International Conference on High Performance Computing & Simulation (HPCS 2016), Innsbruck, Austria, 18-22 July 2016,

Abstract

In this paper, we propose a lock-free architecture to accelerate logic gate circuit simulation using SIMD multi-core machines. We evaluate its performance on different test circuits simulated on the Intel Xeon Phi and 2 other machines. Comparisons are presented of this software/hardware combination with reported performances of GPU and other multi-core simulation platforms. Comparisons are also given between the lock free architecture and a leading commercial simulator running on the same Intel hardware.

• Item Type: Conference Proceedings
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Cockshott, Dr William
• Authors: Chimeh, M. K., and Cockshott, P.
• College/School: College of Science and Engineering > School of Computing Science
• Copyright Holders: Copyright © 2016 Institute of Electrical and Electronics Engineers
• Publisher Policy: Reproduced in accordance with the copyright policy of the publisher

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