InAs FinFETs with Hfin = 20 nm fabricated using a top-down etch process

Oxland, R. et al. (2016) InAs FinFETs with Hfin = 20 nm fabricated using a top-down etch process. IEEE Electron Device Letters, 37(3), pp. 261-264. (doi:10.1109/LED.2016.2521001)

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Abstract

We report the first demonstration of InAs FinFETs with fin width Wfin in the range 25–35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height Hfin = 20 nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length Lg = 1 nm, peak transconductance gm,peak = 1430 µS/µm is measured at Vd = 0.5 V demonstrating that electron transport in InAs fins can match planar devices.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Li, Dr Xu and Thayne, Professor Iain and Oxland, Dr Richard and Thoms, Dr Stephen
Authors: Oxland, R., Li, X., Chang, S.W., Wang, T., Vasen, P., Ramvall, R., Contreras-Guerrero, R., Rojas-Ramirez, J., Holland, M., Doornobos, G., Chang, Y.S., Macintyre, D.S., Thoms, S., Droopad, R., Yeo, Y.-C., Diaz, C.H., Thayne, I.G., and Passlack, M.
College/School:College of Science and Engineering
College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Electron Device Letters
Publisher:Institute of Electrical and Electronics Engineers
ISSN:0741-3106
ISSN (Online):1558-0563
Copyright Holders:Copyright © 2016 IEEE
First Published:First published in IEEE Electron Device Letters 37(3): 261-264
Publisher Policy:Reproduced in accordance with the publisher copyright policy

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