An Intermediate Language and Estimator for Automated Design Space Exploration on FPGAs

Nabi, S. W. and Vanderbauwhede, W. (2015) An Intermediate Language and Estimator for Automated Design Space Exploration on FPGAs. In: HEART2015: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Boston, MA, USA, 1-2 Jun 2015,

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Abstract

We present the TyTra-IR, a new intermediate language intended as a compilation target for high-level language compilers and a front-end for HDL code generators. We develop the requirements of this new language based on the design-space of FPGAs that it should be able to express and the estimation-space in which each configuration from the design-space should be mappable in an automated design flow. We use a simple kernel to illustrate multiple configurations using the semantics of TyTra-IR. The key novelty of this work is the cost model for resource-costs and throughput for different configurations of interest for a particular kernel. Through the realistic example of a Successive Over-Relaxation kernel implemented both in TyTra-IR and HDL, we demonstrate both the expressiveness of the IR and the accuracy of our cost model.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Vanderbauwhede, Dr Wim and Nabi, Dr Syed Waqar
Authors: Nabi, S. W., and Vanderbauwhede, W.
College/School:College of Science and Engineering > School of Computing Science
Journal Name:arXiv
Publisher:arXiv
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