(Invited) towards a vertical and damage free post-etch InGaAs fin profile: dry etch processing, sidewall damage assessment and mitigation options

Peralagu, U. et al. (2015) (Invited) towards a vertical and damage free post-etch InGaAs fin profile: dry etch processing, sidewall damage assessment and mitigation options. ECS Transactions, 69(5), pp. 15-36. (doi:10.1149/06905.0015ecst)

111329.pdf - Accepted Version



Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins.

Item Type:Articles
Keywords:InGaAs, FinFETs, semiconductor etching, semiconductor, capacitance-voltage, dry etching, digital etching, hydrogenation, post-etch cleaning, sidewalls
Glasgow Author(s) Enlighten ID:Steer, Dr Matthew and Li, Dr Xu and Thayne, Professor Iain and Ignatova, Ms Olesya and Peralagu, Mr Uthayasankaran
Authors: Peralagu, U., Li, X., Ignatova, O., Fu, Y.-C., Millar, D. A. J., Steer, M., Povey, I., Hossain, K., Jain, M., Golding, T. G., Droopad, R., Hurley, P. K., and Thayne, I.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Micro- and Nanotechnology (Ultrafast Systems)
Journal Name:ECS Transactions
Journal Abbr.:ECS Trans
Publisher:Electrochemical Society, Inc.
ISSN (Online):1938-6737
Copyright Holders:Copyright © 2015 Electrochemical Society, Inc.
First Published:First published in ECS Transactions 69(5):12-36
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher.

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