Cao, M., Li, X. , Missous, M. and Thayne, I. (2015) Nanoscale molybdenum gates fabricated by low damage inductively coupled plasma SF6/C4F8 etching suitable for high performance compound semiconductor transistors. Microelectronic Engineering, 140, pp. 56-59. (doi: 10.1016/j.mee.2015.06.003)
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Abstract
This paper demonstrates a low damage inductively coupled plasma SF6/C4F8 dry etch process for the realisation of nanoscale molybdenum gate lines. The optimised process is capable of defining 30 nm lines in 100 nm thick molybdenum films, with no observable degradation of the mobility of an InGaAs/InAlAs high electron mobility transistor structure which was subjected to the etch. These characteristics make the process reported here suitable for the realisation of short gate length, high performance III–V compound semiconductor transistors.
Item Type: | Articles |
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Status: | Published |
Refereed: | Yes |
Glasgow Author(s) Enlighten ID: | Li, Dr Xu and Thayne, Prof Iain |
Authors: | Cao, M., Li, X., Missous, M., and Thayne, I. |
College/School: | College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering |
Journal Name: | Microelectronic Engineering |
Publisher: | Elsevier B.V. |
ISSN: | 0167-9317 |
ISSN (Online): | 1873-5568 |
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