New reliability mechanisms in memory design for sub-22nm technologies

Aymerich, N. et al. (2011) New reliability mechanisms in memory design for sub-22nm technologies. In: IEEE 17th International On-Line Testing Symposium (IOLTS), Athens, Greece, 13-15 Jul 2011, pp. 111-114. ISBN 9781457710537 (doi: 10.1109/IOLTS.2011.5993820)

Abstract

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to user's requirements.

• Item Type: Conference Proceedings
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Markov, Dr Stanislav and Wang, Dr Xingsheng and Asenov, Professor Asen
• Authors: Aymerich, N., Asenov, A., Brown, A., Canal, R., Cheng, B., Figueras, J., Gonzalez, A., Herrero, E., Markov, S., Miranda, M., Pouyan, P., Ramirez, T., Rubio, A., Vatajelu, I., Vera, X., Wang, X., and Zuber, P.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• ISBN: 9781457710537