Statistical variability study of a 10nm gate length SOI FinFET device

Cheng, B., Brown, A. R., Wang, X. and Asenov, A. (2012) Statistical variability study of a 10nm gate length SOI FinFET device. In: IEEE: Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, 10-11 Jun 2012, pp. 1-2. ISBN 9781467309967 (doi: 10.1109/SNW.2012.6243343)

Abstract

A comprehensive statistical variability simulation study of a 10nm gate length FinFET device is presented. The FER-induced quantum confinement variation has a consistent impact on all device operation regions; while the RDD induced S/D resistance variation has little impact on the sub-threshold, but has relatively strong impact on the on-current, which is in contrast with the impact of GER on device characteristics. The statistical reliability simulation results indicate that the impact of NBTI/PBTI on individual device is the combined results of trap and fin configurations. Both statistical variability and reliability simulations demonstrate some degree of disentangling between sub-threshold and on-current behaviour. The advantage of FinFET technology is demonstrated by the result of statistical SRAM cell simulation.

• Item Type: Conference Proceedings
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Wang, Dr Xingsheng and Asenov, Professor Asen and Cheng, Dr Binjie
• Authors: Cheng, B., Brown, A. R., Wang, X., and Asenov, A.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• ISSN: 2161-4636
• ISBN: 9781467309967

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