Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance

Amoroso, S. M., Georgiev, V. P. , Gerrer, L., Towie, E., Wang, X., Riddet, C., Brown, A. R. and Asenov, A. (2014) Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance. IEEE Transactions on Electron Devices, 61(12), pp. 4014-4018. (doi: 10.1109/TED.2014.2363212)

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Abstract

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-diffusion with nonequilibrium Green functions simulations, we show that quantum effects in the charge distribution and transport can reduce or amplify the impact of discrete traps in simulation of reliability resilience of scaled FinFETs.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Towie, Dr Ewan and Gerrer, Dr Louis and Georgiev, Dr Vihar and Wang, Dr Xingsheng and Asenov, Professor Asen and Riddet, Mr Craig
Authors: Amoroso, S. M., Georgiev, V. P., Gerrer, L., Towie, E., Wang, X., Riddet, C., Brown, A. R., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Transactions on Electron Devices
Publisher:IEEE
ISSN:0018-9383
ISSN (Online):1557-9646
Copyright Holders:Copyright © 2014 IEEE
First Published:First published in IEEE Transactions on Electron Devices 61(12):4014-4018
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher.

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